UART Protocol Visualizer
Universal Asynchronous Receiver/Transmitter (UART) links send bytes one bit at a time without a clock. The line idles high, a start bit pulls it low, data bits follow least-significant bit first, and the frame closes with optional parity and one or more stop bits. Use the controls below to experiment with different frame layouts and watch how they translate into timing on the TXD line.
Framed Bit Order
UART frames always begin with a start bit (logic 0) and end with stop bits (logic 1). The least significant data bit (D0) leaves the UART first. Parity, when enabled, is inserted after the data bits and before the stop bits.